Data Sheet

V1.4, 2004-04-30

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4

Pin Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1

Power On and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2

Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2.1

Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2.1.1

Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2.1.2

Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2.1.3

Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.1.4

Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.1.5

Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.1.6

Partial Array Self Refresh (PASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.1.7

Temperature Compensated Self Refresh (TCSR) with On-Chip Temperature Sensor . . . . . . . . 15

2.2.1.8

Selectable Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3

State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.4

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4.1

NO OPERATION (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4.2

DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4.3

MODE REGISTER SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.4.4

ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4.5

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4.5.1

READ Burst Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.4.5.2

Clock Suspend Mode for READ Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.4.5.3

READ - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.4.5.4

READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.4.5.5

READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.4.6

WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.4.6.1

WRITE Burst Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.4.6.2

Clock Suspend Mode for WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.4.6.3

WRITE - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.4.6.4

WRITE to READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.4.6.5

WRITE to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.4.7

BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.4.8

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.4.8.1

AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.4.8.2

CONCURRENT AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.4.9

AUTO REFRESH and SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.4.9.1

AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.4.9.2

SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.4.10

POWER DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.4.10.1

DEEP POWER DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.5

Function Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.1

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.2

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.3

Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.4

Pullup and Pulldown Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table of Contents

Data Sheet

V1.4, 2004-04-30

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Figure 1

Standard Ballout 128-Mbit Mobile-RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2

Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3

Power-Up Sequence and Mode Register Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4

State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 5

Address / Command Inputs Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 6

No Operation Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7

Mode Register Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8

Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 9

ACTIVE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10

Bank Activate Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11

READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12

Basic READ Timing Parameters for DQs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 13

Single READ Burst (CAS Latency = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 14

Single READ Burst (CAS Latency = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 15

Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 16

Random READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 17

Non-Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 18

Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 19

Clock Suspend Mode for READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 20

READ Burst - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 21

READ to WRITE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 22

READ to PRECHARGE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 23

WRITE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 24

Basic WRITE Timing Parameters for DQs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 25

WRITE Burst (CAS Latency = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 26

WRITE Burst (CAS Latency = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 27

Consecutive WRITE Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 28

Random WRITE Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 29

Non-Consecutive WRITE Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 30

Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 31

Clock Suspend Mode for WRITE Bursts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 32

WRITE Burst - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 33

WRITE to READ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 34

WRITE to PRECHARGE Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 35

BURST TERMINATE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 36

PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 37

READ with Auto Precharge Interrupted by READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 38

READ with Auto Precharge Interrupted by WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 39

WRITE with Auto Precharge Interrupted by READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 40

WRITE with Auto Precharge Interrupted by WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 41

AUTO REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 42

Auto Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 43

SELF REFRESH Entry Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 44

Self Refresh Entry and Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 45

Power Down Entry Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 46

Power Down Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 47

P-VFBGA-54-2 (Plastic Very Thin Fine Ball Grid Array Package) . . . . . . . . . . . . . . . . . . . . . . . . . 48

List of Figures

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Overview

Data Sheet

V1.4, 2004-04-30

1.3

Description

The HY[B/E]18L128160B[C/F] is a high-speed CMOS, dynamic random-access memory containing

134,217,728

bits. It is internally configured as a quad-bank DRAM.

The HY[B/E]18L128160B[C/F] achieves high speed data transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to the system clock. Read and write accesses are
burst-oriented; accesses start at a selected location and continue for a programmed number of locations (1, 2, 4,
8 or full page) in a programmed sequence.

The device operation is fully synchronous: all inputs are registered at the positive edge of CLK.

The HY[B/E]18L128160B[C/F] is especially designed for mobile applications. It operates from a 1.8V power
supply. Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor
(OCTS); it can further be reduced by using the programmable Partial Array Self Refresh (PASR).

A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep Power-
Down (DPD) mode.

The HY[B/E]18L128160B[C/F] is housed in a 54-ball P-VFBGA package. It is available in Commercial (0

C to

C) and Extended (-25

C to +85

C) temperature range.

Figure 2

Functional Block Diagram

CKE

CLK

RAS
CAS

Addr

s
Re

s
t
er

d
dre

u
x

Ref

r
es

h C

ount

Com

and

Dec

ode

Mode

Registers

ntr

o
l
L

ogi

Bank

Row

s
Lat

c
h

& Dec

o
d

e
r

Bank

o
l
u
m

n
Logi

Column Address

Counter / Latch

Bank 0

Memory Array

(4096 x 512 x 16)

Sense Amplifier

4096

IO Gating

DQM Mask Logic

Column

Decoder

A0-A11

BA0,BA1

DQ0-
DQ15

Data

Output

Reg.

Data

Input

Reg.

LDQM

UDQM

Bank 1

Bank 2

Bank 3

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Overview

Data Sheet

V1.4, 2004-04-30

1.4

Pin Definition and Description

Table 4

Pin Description

Ball

Type

Detailed Function

CLK

Input

Clock: all inputs are sampled on the positive edge of CLK.

CKE

Input

Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals,
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-
DOWN (row active in any bank) or SUSPEND (access in progress). Input buffers,
excluding CLK and CKE are disabled during power-down. Input buffers, excluding CKE
are disabled during SELF REFRESH.

Input

Chip Select: All commands are masked when CS is registered HIGH. CS provides for
external bank selection on systems with multiple memory banks. CS is considered part of
the command code.

RAS, CAS,
WE

Input

Command Inputs: RAS, CAS and WE (along with CS) define the command being
entered.

DQ0 - DQ15

I/O

Data Inputs/Output: Bi-directional data bus (16 bit)

LDQM,
UDQM

Input

Input/Output Mask: input mask signal for WRITE cycles and output enable for READ
cycles. For WRITEs, DQM acts as a data mask when HIGH. For READs, DQM acts as
an output enable and places the output buffers in High-Z state when HIGH (two clocks
latency).
LDQM corresponds to the data on DQ0 - DQ7; UDQM to the data on DQ8 - DQ15.

BA0, BA1

Input

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE
or PRECHARGE command is being applied. BA0, BA1 also determine which mode
register is to be loaded during a MODE REGISTER SET command (MRS or EMRS).

A0 - A11

Input

Address Inputs: A0 - A11 define the row address during an ACTIVE command cycle. A0
- A8 define the column address during a READ or WRITE command cycle. In addition,
A10 (= AP) controls Auto Precharge operation at the end of the burst read or write cycle.
During a PRECHARGE command, A10 (= AP) in conjunction with BA0, BA1 controls
which bank(s) are to be precharged: if A10 is HIGH, all four banks will be precharged
regardless of the state of BA0 and BA1; if A10 is LOW, BA0, BA1 define the bank to be
precharged. During MODE REGISTER SET commands, the address inputs hold the op-
code to be loaded.

DDQ

Supply I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity:

DDQ

= 1.8 V

0.15 V

SSQ

Supply I/O Ground

Supply Power Supply: Power for the core logic and input buffers,

= 1.8 V

0.15 V

Supply Ground

N.C.

No Connect

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

Functional Description

The 128-Mbit Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits.
It is internally configured as a quad-bank DRAM.

READ and WRITE accesses to the Mobile-RAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the banks, A0 - A11
select the row). The address bits registered coincident with the READ or WRITE command are used to select the
starting column location for the burst access.

Prior to normal operation, the Mobile-RAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command description and device operation.

2.1

Power On and Initialization

The Mobile-RAM must be powered up and initialized in a predefined manner (see

Figure 3

). Operational

procedures other than those specified may result in undefined operation.

Figure 3

Power-Up Sequence and Mode Register Sets

Power-up:

VDD and CK stable

Load

Mode

Load

Ext.

Mode

= Don't Care

BA0=L

BA1=H

RFC

MRD

200µs

All

Banks

(High-Z)

DQM

BA0,BA1

NOP

A10

CODE

NOP

CODE

Address

CODE

NOP

CODE

Command

PRE

ARF

MRS

NOP

ACT

MRS

CLK

BA0=L
BA1=L

(H Level)

VDD

VDDQ

CKE

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

1. At first, device core power (V

) and device IO power (V

DDQ

) must be brought up simultaneously. Typically V

and V

DDQ

are driven from a single power converter output.

Assert and hold CKE and DQM to a HIGH level.

2. After V

and V

DDQ

are stable and CKE is HIGH, apply stable clocks.

3. Wait for 200µs while issuing NOP or DESELECT commands.
4. Issue a PRECHARGE ALL command, followed by NOP or DESELECT commands for at least t

period.

5. Issue two AUTO REFRESH commands, each followed by NOP or DESELECT commands for at least t

RFC

period.

6. Issue two MODE REGISTER SET commands for programming the Mode Register and Extended Mode

MRD

period; the order in which both

registers are programmed is not important.

Following these steps, the Mobile-RAM is ready for normal operation.

2.2

Register Definition

2.2.1

Mode Register

The Mode Register is used to define the specific mode of operation of the Mobile-RAM. This definition includes
the selection of a burst length (bits A0-A2), a burst type (bit A3), a CAS latency (bits A4-A6), and a write burst
mode (bit A9). The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it is programmed again or the device loses power.

The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating any subsequent operation. Violating either of these requirements results in unspecified operation.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

MR
Mode Register Definition

(BA[1:0] = 00

)

BA1

BA0

A11

A10

Field

Bits

Type

Description

Write Burst Mode
0

Burst Write

Single Write

[6:4]

CAS Latency
010 2
011 3

Note: All other bit combinations are RESERVED.

Burst Type
0

Sequential

Interleaved

[2:0]

Burst Length
000 1
001 2
010 4
011 8
111 full page (Sequential burst type only)

Note: All other bit combinations are RESERVED.

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

2.2.1.1

Burst Length

READ and WRITE accesses to the Mobile-RAM are burst oriented, with the burst length being programmable. The
burst length determines the maximum number of column locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4, 8 locations are available for both the sequential and interleaved burst
types, and a full-page burst mode is available for the sequential burst type.

When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary
is reached. The block is uniquely selected by A1-A8 when the burst length is set to two, by A2-A8 when the burst
length is set to four and by A3-A8 when the burst length is set to eight. The remaining (least significant) address
bit(s) is (are) used to select the starting location within the block.

Full page bursts wrap within the page if the boundary is reached. Please note that full page bursts do not self-
terminate; this implies that full-page read or write bursts with Auto Precharge are not legal commands.

Notes

1. For a burst length of 2, A1-Ai select the two-data-element block; A0 selects the first access within the block.
2. For a burst length of 4, A2-Ai select the four-data-element block; A0-A1 select the first access within the block.
3. For a burst length of 8, A3-Ai select the eight-data-element block; A0-A2 select the first access within the block.
4. For a full page burst, A0-Ai select the starting data element.
5. Whenever a boundary of the block is reached within a given sequence, the following access wraps within the

block.

2.2.1.2

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in

Table 5

Burst Definition

Burst Length

Starting Column Address

Order of Accesses Within a Burst

Sequential

Interleaved

0 - 1

1 - 0

0 - 1 - 2 - 3

1 - 2 - 3 - 0

1 - 0 - 3 - 2

2 - 3 - 0 - 1

3 - 0 - 1 - 2

3 - 2 - 1 - 0

0 - 1 - 2 - 3 - 4 - 5 - 6 - 7

1 - 2 - 3 - 4 - 5 - 6 - 7 - 0

1 - 0 - 3 - 2 - 5 - 4 - 7 - 6

2 - 3 - 4 - 5 - 6 - 7 - 0 - 1

2 - 3 - 0 - 1 - 6 - 7 - 4 - 5

3 - 4 - 5 - 6 - 7 - 0 - 1 - 2

3 - 2 - 1 - 0 - 7 - 6 - 5 - 4

4 - 5 - 6 - 7 - 0 - 1 - 2 - 3

5 - 6 - 7 - 0 - 1 - 2 - 3 - 4

5 - 4 - 7 - 6 - 1 - 0 - 3 - 2

6 - 7 - 0 - 1 - 2 - 3 - 4 - 5

6 - 7 - 4 - 5 - 2 - 3 - 0 - 1

7 - 0 - 1 - 2 - 3 - 4 - 5 - 6

7 - 6 - 5 - 4 - 3 - 2 - 1 - 0

Full Page

Cn, Cn+1, Cn+2, ...

not supported

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

2.2.1.3

Read Latency

The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a READ command and
the availability of the first piece of output data. The latency can be programmed to 2 or 3 clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available with clock
edge n + m (for details please refer to the READ command description).

2.2.1.4

Write Burst Mode

When A9 = 0, the burst length programmed via A0-A2 applies to both read and write bursts; when A9 = 1, write
accesses consist of single data elements only.

2.2.1.5

Extended Mode Register

The Extended Mode Register controls additional low power features of the device. These include the Partial Array
Self Refresh (PASR, bits A0-A2)), the Temperature Compensated Self Refresh (TCSR, bits A3-A4)) and the drive
strength selection for the DQs (bits A5-A6). The Extended Mode Register is programmed via the MODE
REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored information until it is programmed
again or the device loses power.

The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified
time before initiating any subsequent operation. Violating either of these requirements result in unspecified
operation.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

2.2.1.6

Partial Array Self Refresh (PASR)

Partial Array Self Refresh is a power-saving feature specific to Mobile RAMs. With PASR, self refresh may be
restricted to variable portions of the total array. The selection comprises all four banks (default), two banks, one
bank, half of one bank, and a quarter of one bank. Data written to the non activated memory sections will get lost
after a period defined by

REF

(cf.

Table 13

EMR
Extended Mode Register

(BA[1:0] = 10

)

BA1

BA0

A11

A10

(TCSR)

PASR

Field

Bits

Type

Description

[6:5]

Selectable Drive Strength
00

Full Drive Strength

Half Drive Strength

Note: All other bit combinations are RESERVED.

TCSR

[4:3]

Temperature Compensated Self Refresh
XX

Superseded by on-chip temperature sensor (see text)

PASR [2:0]

Partial Array Self Refresh
000 all banks
001 1/2 array (BA1 = 0)
010 1/4 array (BA1 = BA0 = 0)
101 1/8 array (BA1 = BA0 = RA11 = 0)
110 1/16 array (BA1 = BA0 = RA11 = RA10 = 0)

Note: All other bit combinations are RESERVED.

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

2.2.1.7

Temperature Compensated Self Refresh (TCSR) with On-Chip Temperature
Sensor

DRAM devices store data as electrical charge in tiny capacitors that require a periodic refresh in order to retain
the stored information. This refresh requirement heavily depends on the die temperature: high temperatures
correspond to short refresh periods, and low temperatures correspond to long refresh periods.

The Mobile-RAM is equipped with an on-chip temperature sensor which continuously senses the actual die
temperature and adjusts the refresh period in Self Refresh mode accordingly. This makes any programming of the
TCSR bits in the Extended Mode Register obsolete. It also is the superior solution in terms of compatibility and
power-saving, because

it is fully compatible to all processors that do not support the Extended Mode Register

it is fully compatible to all applications that only write a default (worst case) TCSR value, e.g. because of the
lack of an external temperature sensor

it does not require any processor interaction for regular TCSR updates

2.2.1.8

Selectable Drive Strength

The drive strength of the DQ output buffers is selectable via bits A5 and A6. The default value ("half drive strength")
is suitable for typical applications of a Mobile-RAM. For heavier loaded systems, a stronger output buffer ("full drive
strength") is available.

curves for the full drive strength and half drive strength are included in this document.

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

2.4

Commands

Address (A0 - A11, BA0, BA1), write data (DQ0 - DQ15) and command inputs (CKE, CS, RAS, CAS, WE, DQM)
are all registered on the positive edge of CLK.

Figure 5

shows the basic timing parameters, which apply to all

commands and operations.

Figure 5

Address / Command Inputs Timing Parameters

Table 6

Command Overview

Command

CS RAS CAS WE DQM

Address

Notes

NOP

DESELECT

1) DESELECT and NOP are functionally interchangeable.

NO OPERATION

ACT

ACTIVE (Select bank and row)

Bank / Row

2) BA0, BA1 provide bank address, and A0 - A11 provide row address.

READ (Select bank and column and start read burst)

L/H

Bank / Col

3) BA0, BA1 provide bank address, A0 - A8 provide column address; A10 HIGH enables the Auto Precharge feature

(nonpersistent), A10 LOW disables the Auto Precharge feature.

WRITE (Select bank and column and start write burst)

L/H

Bank / Col

BST

BURST TERMINATE or
DEEP POWER DOWN

4) This command is BURST TERMINATE if CKE is HIGH, DEEP POWER DOWN if CKE is LOW. The BURST TERMINATE

command is defined for READ or WRITE bursts with Auto Precharge disabled only.

PRE

PRECHARGE (Deactivate row in bank or banks)

Code

5) A10 LOW:

BA0, BA1

determine which bank is precharged.

A10 HIGH: all banks are precharged and

BA0, BA1

are "Don't Care".

ARF

AUTO REFRESH or
SELF REFRESH (enter self refresh mode)

6)7)

6) This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7) Internal refresh counter controls row and bank addressing; all inputs and I/Os are "Don't Care" except for CKE.

MRS

MODE REGISTER SET

Op-Code

8) BA0, BA1 select either the Mode Register (BA0 = 0, BA1 = 0) or the Extended Mode Register (BA0 = 0, BA1 = 1); other

combinations of BA0, BA1 are reserved; A0 - A11 provide the op-code to be written to the selected mode register.

Data Write / Output Enable

9) DQM LOW: data present on DQs is written to memory during write cycles; DQ output buffers are enabled during read

cycles;
DQM HIGH: data present on DQs are masked and thus not written to memory during write cycles; DQ output buffers are
placed in High-Z state (two clocks latency) during read cycles.

Write Mask / Output Disable (High-Z)

= Don't Care

CLK

Input *)

Valid

*) = A0 - A11, BA0, BA1, CS, CKE, RAS, CAS, WE

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

During READ bursts, the valid data-out element from the starting column address is available following the CAS
latency after the READ command. Each subsequent data-out element is valid nominally at the next positive clock
edge. Upon completion of a READ burst, assuming no other READ command has been initiated, the DQs go to
High-Z state.

Figure 13

and

Figure 14

show single READ bursts for each supported CAS latency setting.

Figure 13

Single READ Burst (CAS Latency = 2)

Table 10

Timing Parameters for READ

Parameter

Symbol

- 7.5

Units

Notes

min.

max.

Access time from CLK

CL = 3

5.4

CL = 2

6.0

DQ low-impedance time from CLK

1.0

DQ high-impedance time from CLK

3.0

7.0

Data out hold time

2.5

DQM to DQ High-Z delay (READ Commands)

DQZ

ACTIVE to ACTIVE command period

ACTIVE to READ or WRITE delay

RCD

ACTIVE to PRECHARGE command period

RAS

100k

PRECHARGE command period

1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:

no. of clock cycles = specified delay / clock period; round up to next integer.

Ba A, Col n = bank A, column n
DO n = Data Out from column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data Out are provided in the programmed order following DO n.

= Don't Care

CL=2

RCD

RAS

CLK

Command

NOP

READ

NOP

PRE

NOP

ACT

Address

Ba A,

Row b

Ba A,

Col n

Ba A,

Row x

A10 (AP)

Pre Bank A

Pre All

Dis AP

Row x

Row b

DO n+1

DO n

DO n+2

DO n+3

AP = Auto Precharge
Dis AP = Disable Auto Precharge

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

Figure 14

Single READ Burst (CAS Latency = 3)

Data from any READ burst may be concatenated with data from a subsequent READ command. In either case, a
continuous flow of data can be maintained. A READ command can be initiated on any clock cycle following a
previous READ command, and may be performed to the same or a different (active) bank. The first data element
from the new burst follows either the last element of a completed burst (

Figure 15

) or the last desired data element

of a longer burst which is being truncated (

Figure 16

). The new READ command should be issued x cycles after

the first READ command, where x equals the number of desired data elements.

Figure 15

Consecutive READ Bursts

Ba A, Col n = bank A, column n
DO n = Data Out from column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data Out are provided in the programmed order following DO n.

= Don't Care

CL=3

RCD

RAS

Command

NOP

READ

NOP

PRE

NOP

ACT

NOP

CLK

AP = Auto Precharge
Dis AP = Disable Auto Precharge

Address

A10 (AP)

Pre Bank A

Pre All

Dis AP

DO n+1

DO n

DO n+2

DO n+3

Ba A,

Row b

Ba A,

Row x

Ba A,

Col n

Ba A, Col n (b) = Bank A, Column n (b)
DO n (b) = Data Out from column n (b)
Burst Length = 4 in the case shown.
3 subsequent elements of Data Out are provided in the programmed order following DO n (b).

= Don't Care

CLK

CL=2

CL=3

Command

NOP

READ

NOP

READ

NOP

Address

Ba A,

Col b

Ba A,

Col n

DO n+1

DO n

DO n+2

DO n+3

DO b+2

DO b

DO b+1

DO n+1

DO n

DO n+2

DO n+3

DO b+1

DO b

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

2.4.5.1

READ Burst Termination

Data from any READ burst may be truncated using the BURST TERMINATE command (see

Page 33

), provided

that Auto Precharge was not activated. The BURST TERMINATE latency is equal to the CAS latency, i.e. the
BURST TERMINATE command must be issued x clock cycles before the clock edge at which the last desired data
element is valid, where x equals the CAS latency for READ bursts minus 1. This is shown in

Figure 18

. The

BURST TERMINATE command may be used to terminate a full-page READ which does not self-terminate.

Figure 18

Terminating a READ Burst

2.4.5.2

Clock Suspend Mode for READ Cycles

Clock suspend mode allows to extend any read burst in progress by a variable number of clock cycles. As long as
CKE is registered LOW, the following internal clock pulse(s) will be ignored and data on DQ will remain driven, as
shown in

Figure 19

Clock Suspend Mode for READ Bursts

Ba A, Col n = Bank A, Column n
DO n = Data Out from column n
Burst Length = 4 in the case shown.
2 subsequent elements of Data Out are provided in the programmed order following DO n.
The burst is terminated after the 3rd data element.

= Don't Care

CLK

CL=2

CL=3

Command

NOP

READ

NOP

BST

NOP

Address

Ba A,

Col n

DO n+1

DO n

DO n+2

DO n+1

DO n

DO n+2

Ba A, Col n etc. = Bank A, Column n etc.
DO n etc. = Data Out from column n etc.
CL = 2 in the case shown
Clock suspend latency t

CSL

is 1 clock cycle

= Don't Care

CLK

CSL

CKE

internal

clock

Command

READ

NOP

Ba A,

Col n

Address

DO n+2

DO n

DO n+1

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

2.4.5.3

READ - DQM Operation

DQM may be used to suppress read data and place the output buffers into High-Z state. The generic timing
parameters as listed in

Table 10

also apply to this DQM operation. The read burst in progress is not affected and

will continue as programmed.

Figure 20

READ Burst - DQM Operation

2.4.5.4

READ to WRITE

A READ burst may be followed by or truncated with a WRITE command. The WRITE command can be performed
to the same or a different (active) bank. Care must be taken to avoid bus contention on the DQs; therefore it is
recommended that the DQs are held in High-Z state for a minimum of 1 clock cycle. This can be achieved by either
delaying the WRITE command, or suppressing the data-out from the READ by pulling DQM HIGH two clock cycles
prior to the WRITE command, as shown in

Figure 21

. With the registration of the WRITE command, DQM acts as

a write mask: when asserted HIGH, input data will be masked and no write will be performed.

Figure 21

READ to WRITE Timing

Ba A, Col n = bank A, column n
DO n = Data Out from column n
CL = 2 in the case shown.
DQM read latency t

DQZ

is 2 clock cycles

= Don't Care

CLK

Command

NOP

READ

NOP

DQM

DQZ

Address

Ba A,

Col n

DO n+2

DO n

DO n+3

Ba A, Col n (b) = bank A, column n (b)
DO n = Data Out from column n; DI b = Data In to column b;
DQM is asserted HIGH to set DQs to High-Z state for 1 clock cycle prior to the WRITE command.

= Don't Care

CLK

CL=2

CL=3

Command

NOP

READ

NOP

WRITE

Address

Ba A,

Col b

Ba A,

Col n

DQM

DO n

DI b

DI b+1

DO n+1

High-Z

DI b+2

DI b

DI b+1

DO n

High-Z

DI b+2

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

2.4.5.5

READ to PRECHARGE

A READ burst may be followed by, or truncated with a PRECHARGE command to the same bank, provided that
Auto Precharge was not activated. This is shown in

Figure 22

The PRECHARGE command should be issued x clock cycles before the clock edge at which the last desired data
element is valid, where x equals the CAS latency for READ bursts minus 1. Following the PRECHARGE
command, a subsequent ACTIVE command to the same bank cannot be issued until

is met. Please note that

part of the row precharge time is hidden during the access of the last data elements.

In the case of a READ being executed to completion, a PRECHARGE command issued at the optimum time (as
described above) provides the same operation that would result from the same READ burst with Auto Precharge
enabled. The disadvantage of the PRECHARGE command is that it requires that the command and address
busses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command
is that it can be used to truncate bursts.

Figure 22

READ to PRECHARGE Timing

Ba A, Col n = bank A, column n; BA Am Row = bank A, row x
DO n = Data Out from column n
Burst Length = 4 in the case shown.
CAS latency = 3 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO n.

= Don't Care

CL=3

CLK

Command

NOP

READ

NOP

ACT

PRE

Ba A,

Row a

Address

Ba A

Ba A,

Col n

Dis AP

Pre Bank A

Pre All

A10

(AP)

DO n+1

DO n

DO n+2

DO n+3

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

Figure 25

WRITE Burst (CAS Latency = 2)

Figure 26

WRITE Burst (CAS Latency = 3)

Table 11

Timing Parameters for WRITE

Parameter

Symbol

- 7.5

Units

Notes

min.

max.

DQ and DQM input setup time

1.5

DQ and DQM input hold time

0.8

DQM write mask latency

DQW

ACTIVE to ACTIVE command period

ACTIVE to READ or WRITE delay

RCD

ACTIVE to PRECHARGE command period

RAS

100k

WRITE recovery time

PRECHARGE command period

1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:

no. of clock cycles = specified delay / clock period; round up to next integer.

Ba A, Col n = bank A, column n
DI n = Data In to column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following DI n.

= Don't Care

CLK

RCD

RAS

Command

NOP

WRITE

NOP

PRE

NOP

ACT

NOP

Address

Ba A,

Row x

Ba A,

Col n

Ba A,

Row b

Row x

Row b

Dis

Pre Bank A

Pre All

A10 (AP)

DI n

DI n+2

DI n+3

DI n+1

Ba A, Col n = bank A, column n
DI n = Data In to column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following DI n.

= Don't Care

RCD

RAS

CLK

Command

NOP

WRITE

NOP

PRE

NOP

ACT

NOP

Address

Ba A,

Row n

Ba A,

Col n

Ba A,

Row b

Pre Bank A

Pre All

Row

Dis

Row

A10 (AP)

DI n

DI n+2

DI n+3

DI n+1

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either
case, a continuous flow of input data can be maintained. A WRITE command can be issued on any positive edge
of clock following the previous WRITE command. The first data element from the new burst is applied after either
the last element of a completed burst (

Figure 27

) or the last desired data element of a longer burst which is being

truncated (

Figure 28

). The new WRITE command should be issued x cycles after the first WRITE command,

where x equals the number of desired data elements.

Figure 27

Consecutive WRITE Bursts

Figure 28

Random WRITE Bursts

Non-consecutive WRITE bursts are shown in

Figure 29

Non-Consecutive WRITE Bursts

Ba A, Col n (b) = Bank A, Column n (b)
DI n (b) = Data In to column n (b)
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following DI n (b).

Command

NOP

WRITE

CLK

Address

Ba A,

Col b

Ba A,

Col n

DI n

DI n+1

DI n+2

DI n+3

DI b

DI b+1

DI b+2

DI b+3

= Don't Care

Ba A, Col n etc. = Bank A, Column n etc.
DI n etc. = Data In to column n etc.
Burst Length = 4 in the case shown; bursts are terminated by consecutive WRITE commands.
3 subsequent elements of Data In are provided in the programmed order following DI m .

= Don't Care

CLK

Command

NOP

WRITE

Address

Ba A,

Col m

Ba A,

Col x

Ba A,

Col a

Ba A,

Col n

DI n

DI a

DI x

DI m

DI m+1

DI m+2

DI m+3

Ba A, Col n (b) = Bank A, Column n (b)
DI n (b) = Data In to column n (b)
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following DI n (b).

= Don't Care

CLK

WRITE

Command

NOP

WRITE

Ba A,

Col n

Address

Ba A,

Col b

DI b

DI n

DI n+1

DI n+2

DI n+3

DI b+1

DI b+2

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

2.4.6.1

WRITE Burst Termination

Data from any WRITE burst may be truncated using the BURST TERMINATE command (see

Page 33

), provided

that Auto Precharge was not activated. The input data provided coincident with the BURST TERMINATE
command will be ignored. This is shown in

Figure 30

. The BURST TERMINATE command may be used to

terminate a full-page WRITE which does not self-terminate.

Figure 30

Terminating a WRITE Burst

2.4.6.2

Clock Suspend Mode for WRITE Cycles

Clock suspend mode allows to extend any WRITE burst in progress by a variable number of clock cycles. As long
as CKE is registered LOW, the following internal clock pulse(s) will be ignored and no data will be captured, as
shown in

Figure 31

Clock Suspend Mode for WRITE Bursts

Ba A, Col n = Bank A, Column n
DI n = Data In to column n
Burst Length = 4 in the case shown.
2 subsequent elements of Data In are written in the programmed order following DI n.
The burst is terminated after the 3rd data element.

= Don't Care

CLK

Command

NOP

BST

NOP

WRITE

NOP

Address

Ba A,

Col n

DI n

DI n+1

DI n+2

Ba A, Col n etc. = Bank A, Column n etc.
DO n etc. = Data Out from column n etc.
CL = 2 in the case shown
Clock suspend latency t

CSL

is 1 clock cycle

CLK

CKE

internal

clock

Command

NOP

WRITE

NOP

Ba A,

Col n

Address

DI n+2

DI n

DI n+1

= Don't Care

CSL

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

2.4.6.3

WRITE - DQM Operation

DQM may be used to mask write data: when asserted HIGH, input data will be masked and no write will be
performed. The generic timing parameters as listed in

Table 11

also apply to this DQM operation. The write burst

in progress is not affected and will continue as programmed.

Figure 32

WRITE Burst - DQM Operation

2.4.6.4

WRITE to READ

A WRITE burst may be followed by, or truncated with a READ command. The READ command can be performed
to the same or a different (active) bank. With the registration of the READ command, data inputs will be ignored
and no WRITE will be performed, as shown in

Figure 33

WRITE to READ Timing

Ba A, Col n = Bank A, Column n
DI n = Data In to column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following
DI n, with the first element (DI n+1) being masked.
DQM write latency is 0 clock cycles.

= Don't Care

CLK

Command

NOP

WRITE

Address

Ba A,

Col n

DQM

DI n

DI n+2

DI n+3

Ba A, Col n (b) = bank A, column n (b)
DI n = Data In to column n; DO b = Data Out from column b;
Burst Length = 4 in the case shown.
3 subsequent elements of Data In (Out) are provided in the programmed order following DI n (DO b).
DI n+3 is ignored due to READ command. No DQM masking required at this point.

= Don't Care

CLK

Write data

are ignored

CL=2

CL=3

Command

NOP

READ

NOP

WRITE

Address

Ba A,

Col b

Ba A,

Col n

DO b

DO b+1

DO b+2

DI n

DI n+1

DI n+2

High-Z

DO b

DI b+1

DI n

DI n+1

DI n+2

High-Z

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

2.4.6.5

WRITE to PRECHARGE

A WRITE burst may be followed by, or truncated with a PRECHARGE command to the same bank, provided that
Auto Precharge was not activated. This is shown in

Figure 34

The PRECHARGE command should be issued

after the clock edge at which the last desired data element of

the WRITE burst was registered. Additionally, when truncating a WRITE burst, DQM must be pulled to mask input
data presented during

prior to the PRECHARGE command. Following the PRE-CHARGE command, a

subsequent ACTIVE command to the same bank cannot be issued until

is met.

In the case of a WRITE being executed to completion, a PRECHARGE command issued at the optimum time (as
described above) provides the same operation that would result from the same WRITE burst with Auto Precharge
enabled. The disadvantage of the PRECHARGE command is that it requires that the command and address
busses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command
is that it can be used to truncate bursts.

Figure 34

WRITE to PRECHARGE Timing

2.4.7

BURST TERMINATE

Figure 35

BURST TERMINATE Command

Ba A, Col n = bank A, column n
DI n = Data In to column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following DI n.
DI n+3 is masked due to DQM pulled HIGH during t

period prior to PRECHARGE command.

= Don't Care

DI n

DI n+1

DI n+2

CLK

DQM

Command

NOP

ACT

PRE

WRITE

Address

Ba A,

Col n

Ba A,

Row a

Ba A

Dis AP

Pre Bank A

Pre All

A10

(AP)

AP = Auto Precharge
Dis AP = Disable Auto Precharge

= Don't Care

CAS

CKE

(High)

CLK

A0-A11

BA0,BA1

RAS

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

The BURST TERMINATE command is used to truncate READ or WRITE bursts (with Auto Precharge disabled).
The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be
truncated, as shown in

Figure 18

and

Figure 30

, respectively.

The BURST TERMINATE command is not allowed for truncation of READ or WRITE bursts with Auto Precharge
enabled.

2.4.8

PRECHARGE

Figure 36

PRECHARGE Command

The PRECHARGE command is used to deactivate (close) the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent row access a specified time (

) after the PRECHARGE

command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where
only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't
Care".

Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row
in that bank, or if the previously open row is already in the process of precharging.

2.4.8.1

AUTO PRECHARGE

Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but
without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction
with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or
WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto Precharge is
nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto Precharge
ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another
command to the same bank until the precharge (

) is completed. This is determined as if an explicit

PRECHARGE command was issued at the earliest possible time, as described for each burst type.

BA0,BA1

CKE

(High)

CLK

= Don't Care

BA = Bank Address
(if A10 = L, otherwise Don't Care)

RAS

CAS

A10

One Bank

All Banks

A0-A9

A11

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

2.4.8.2

CONCURRENT AUTO PRECHARGE

A READ or WRITE burst with Auto Precharge enabled can be interrupted by a subsequent READ or WRITE
command issued to a different bank.

Figure 37

shows a READ with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge)

to bank m. The READ to bank m will interrupt the READ to bank n, CAS latency later. The precharge to bank n
will begin when the READ to bank m is registered.

Figure 38

shows a READ with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto Precharge)

to bank m. The precharge to bank n will begin when the WRITE to bank m is registered. DQM should be pulled
HIGH two clock cycles prior to the WRITE to prevent bus contention.

Figure 39

shows a WRITE with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge)

to bank m. The precharge to bank n will begin

after the new command to bank m is registered. The last valid

data-in to bank n is one clock cycle prior to the READ to bank m.

Figure 40

shows a WRITE with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto

Precharge) to bank m. The precharge to bank n will begin

after the WRITE to bank m is registered. The last

valid data-in to bank n is one clock cycle prior to the WRITE to bank m.

Figure 37

READ with Auto Precharge Interrupted by READ

Figure 38

READ with Auto Precharge Interrupted by WRITE

RD-AP = Read with Auto Precharge; READ = Read with or without Auto Precharge
CL = 2 and Burst Length = 4 in the case shown
Read with Auto Precharge to bank n is interrupted by subsequent Read to bank m

= Don't Care

CL=2

CLK

Command

RD-AP

NOP

READ

NOP

Address

Bank n

Col b

Bank m

Col x

DO b+1

DO b

DO x

DO x+1

DO x+2

(bank n)

RD-AP = Read with Auto Precharge; WRITE = Write with or without Auto Precharge
CL = 2 and Burst Length = 4 in the case shown
Read with Auto Precharge to bank n is interrupted by subsequent Write to bank m

= Don't Care

CL=2

DQM

CLK

Command

NOP

RD-AP

NOP

WRITE

NOP

Address

Bank m

Col x

Bank n

Col b

DO b

DI x+1

DI x+2

DI x+3

DI x

(bank n)

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

Figure 46

Power Down Entry and Exit

2.4.10.1

DEEP POWER DOWN

The deep power down mode is an unique function on Low Power SDRAM devices with extremely low current
consumption. Deep power down mode is entered using the BURST TERMINATE command (cf.

Figure 35

) except

that CKE is LOW. All internal voltage generators inside the device are stopped and all memory data is lost in this
mode. To enter the deep power down mode all banks must be precharged.

The deep power down mode is asynchronously exited by asserting CKE HIGH. After the exit, the same command
sequence as for power-up initialization, including the 200µs initial pause, has to be applied before any other
command may be issued (cf.

Figure 3

and

Figure 4

2.5

Function Truth Tables

Table 14

Current State Bank n - Command to Bank n

Current State

RAS CAS

WE Command / Action

Notes

Any

DESELECT (NOP / continue previous operation)

1)2)3)4)5)6)

NO OPERATION (NOP / continue previous operation)

1) to 6)

Idle

ACTIVE (select and activate row)

1) to 6)

AUTO REFRESH

1) to 7)

MODE REGISTER SET

1) to 7)

PRECHARGE

1) to 6), 8)

Row Active

READ (select column and start READ burst)

1) to 6), 9)

WRITE (select column and start WRITE burst)

1) to 6), 9)

PRECHARGE (deactivate row in bank or banks)

1) to 6), 10)

Read
(Auto-
Precharge
Disabled)

READ (select column and start new READ burst)

1) to 6), 9)

WRITE (select column and start new WRITE burst)

1) to 6), 9)

PRECHARGE (truncate READ burst, start precharge)

1) to 6), 10)

BURST TERMINATE

1) to 6), 11)

= Don't Care

Precharge Power Down mode shown: all banks are idle and tRP met
when Power Down Entry Command is issued

Any

Command

Power Down

Entry

Exit from

Power Down

High-Z

A10 (AP)

Valid

Pre All

Address

Valid

Command

NOP

Valid

PRE

CKE

CLK

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

Write
(Auto-
Precharge
Disabled)

READ (select column and start READ burst)

1) to 6), 9)

WRITE (select column and start WRITE burst)

1) to 6), 9)

PRECHARGE (truncate WRITE burst, start precharge)

1) to 6), 10)

BURST TERMINATE

1) to 6), 11)

1) This table applies when CKEn-1 was HIGH and CKEn is HIGH and after

has been met (if the previous state was self

refresh).

2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are

those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

3) Current state definitions:

Idle:

The bank has been precharged, and

has been met.

Row Active:

A row in the bank has been activated, and

RCD

has been met. No data bursts/accesses and no register

accesses are in progress.

Read:

A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been
terminated.

Write:

A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been
terminated.

4) The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or

allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable
commands to the other bank are determined by its current state and according to

Table 15

Precharging:

Starts with registration of a PRECHARGE command and ends when

is met. Once

is met, the bank

is in the "idle" state.

Row Activating: Starts with registration of an ACTIVE command and ends when

RCD

is met. Once

RCD

is met, the bank

is in the "row active" state.

Read with AP
Enabled:

Starts with registration of a READ command with Auto Precharge enabled and ends when

has been

met. Once

is met, the bank is in the idle state.

Write with AP
Enabled:

Starts with registration of a WRITE command with Auto Precharge enabled and ends when

has been

met. Once

is met, the bank is in the idle state.

5) The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied

on each positive clock edge during these states.
Refreshing:

Starts with registration of an AUTO REFRESH command and ends when

is met. Once

is met, the

SDRAM is in the "all banks idle" state.

Accessing Mode
Register:

Starts with registration of a MODE REGISTER SET command and ends when

MRD

has been met. Once

MRD

is met, the SDRAM is in the "all banks idle" state.

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when

is met. Once

is met, all

banks are in the idle state.

6) All states and sequences not shown are illegal or reserved.

7) Not bank-specific; requires that all banks are idle and no bursts are in progress.

8) Same as NOP command in that state.

9) READs or WRITEs listed in the Command/Action column include READs or WRITEs with Auto Precharge enabled and

READs or WRITEs with Auto Precharge disabled.

10) May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.

11) Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.

Table 15

Current State Bank n - Command to Bank m (different bank)

Current State

RAS CAS

WE Command / Action

Notes

Any

DESELECT (NOP / continue previous operation)

1)2)3)4)5)6)

NO OPERATION (NOP / continue previous operation)

1) to 6)

Table 14

Current State Bank n - Command to Bank n (cont'd)

Current State

RAS CAS

WE Command / Action

Notes

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

Idle

Any command otherwise allowed to bank n

1) to 6)

Row Activating,
Active, or
Precharging

ACTIVE (select and activate row)

1) to 6)

READ (select column and start READ burst)

1) to 7)

WRITE (select column and start WRITE burst)

1) to 7)

PRECHARGE (deactivate row in bank or banks)

1) to 6)

Read (Auto-
Precharge
Disabled)

ACTIVE (select and activate row)

1) to 6)

READ (select column and start READ burst)

1) to 7)

WRITE (select column and start WRITE burst)

1) to 8)

PRECHARGE (deactivate row in bank or banks)

1) to 6)

Write (Auto-
Precharge
Disabled)

ACTIVE (select and activate row)

1) to 6)

READ (select column and start READ burst)

1) to 7)

WRITE (select column and start WRITE burst)

1) to 7)

PRECHARGE (deactivate row in bank or banks)

1) to 6)

Read
(with Auto-
Precharge)

ACTIVE (select and activate row)

1) to 6)

READ (select column and start READ burst)

1) to 7), 9)

WRITE (select column and start WRITE burst)

1) to 9)

PRECHARGE (deactivate row in bank or banks)

1) to 6)

Write
(with Auto-
Precharge)

ACTIVE (select and activate row)

1) to 6)

READ (select column and start READ burst)

1) to 7), 9)

WRITE (select column and start WRITE burst)

1) to 7), 9)

PRECHARGE (deactivate row in bank or banks)

1) to 6)

1) This table applies when CKEn-1 was HIGH and CKEn is HIGH and after

has been met (if the previous state was Self

Refresh).

2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands

shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is
allowable). Exceptions are covered in the notes below.

3) Current state definitions:

Idle:

The bank has been precharged, and

has been met.

Row Active:

A row in the bank has been activated, and

RCD

has been met. No data bursts/accesses and no register

accesses are in progress.

Read:

A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been
terminated.

Write:

A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been
terminated.

Read with AP
Enabled:

Starts with registration of a READ command with Auto Precharge enabled and ends when

has been

met. Once

is met, the bank is in the idle state.

Write with AP
Enabled:

Starts with registration of a WRITE command with Auto Precharge enabled and ends when

has been

met. Once

is met, the bank is in the idle state.

4) AUTO REFRESH, SELF REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle.

5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state

only.

6) All states and sequences not shown are illegal or reserved.

7) READs or WRITEs listed in the Command/Action column include READs or WRITEs with Auto Precharge enabled and

READs or WRITEs with Auto Precharge disabled.

8) Requires appropriate DQM masking.

Table 15

Current State Bank n - Command to Bank m (different bank) (cont'd)

Current State

RAS CAS

WE Command / Action

Notes

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Functional Description

Data Sheet

V1.4, 2004-04-30

9) Concurrent Auto Precharge: bank n will start precharging when its burst has been interrupted by a READ or WRITE

command to bank m.

Table 16

Truth Table - CKE

CKEn-1

CKEn

Current State

Command

Action

Notes

Power Down

Maintain Power Down

1)2)3)4)

1) CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.

2) Current state is the state immediately prior to clock edge n.

3) COMMAND n is the command registered at clock edge n; ACTION n is a result of COMMAND n.

4) All states and sequences not shown are illegal or reserved.

Self Refresh

Maintain Self Refresh

1) to 4)

Clock Suspend

Maintain Clock Suspend

1) to 4)

Deep Power Down

Maintain Deep Power
Down

1) to 4)

Power Down

DESELECT or NOP

Exit Power Down

1) to 4)

Self Refresh

DESELECT or NOP

Exit Self Refresh

1) to 5)

5) DESELECT or NOP commands should be issued on any clock edges occurring during

period.

Clock Suspend

Exit Clock Suspend

1) to 4)

Deep Power Down

Exit Deep Power Down

1) to 4), 6)

6) Exit from DEEP POWER DOWN requires the same command sequence as for power-up initialization.

All Banks Idle

DESELECT or NOP

Enter Precharge Power
Down

1) to 4)

Bank(s) Active

DESELECT or NOP

Enter Active Power Down

1) to 4)

All Banks Idle

AUTO REFRESH

Enter Self Refresh

1) to 4)

Read / Write burst

(valid)

Enter Clock Suspend

1) to 4)

see

Table 14

and

Table 15

1) to 4)

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Electrical Characteristics

Data Sheet

V1.4, 2004-04-30

Electrical Characteristics

3.1

Operating Conditions

Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.

Table 17

Absolute Maximum Ratings

Parameter

Symbol

Values

Unit

min.

max.

Power Supply Voltage

-0.3

2.7

Power Supply Voltage for Output Buffer

DDQ

-0.3

2.7

Input Voltage

-0.3

DDQ

+ 0.3

Output Voltage

OUT

-0.3

DDQ

+ 0.3

Operation Case Temperature

Commercial

+70

Extended

-25

+85

Storage Temperature

STG

-55

+150

Power Dissipation

0.7

Short Circuit Output Current

OUT

Table 18

Pin Capacitances

1)2)

1) These values are not subject to production test but verified by device characterization.

2) Input capacitance is measured according to JEP147 with VDD, VDDQ applied and all other pins (except the pin under test)

floating. DQ's should be in high impedance state. This may be achieved by pulling CKE to low level.

Parameter

Symbol

Values

Unit

min.

max.

Input capacitance: CLK

1.5

3.0

Input capacitance: all other input pins

1.5

3.0

Input/Output capacitance: DQ

3.0

5.0

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Electrical Characteristics

Data Sheet

V1.4, 2004-04-30

3.2

AC Characteristics

Table 20

AC Characteristics

1)2)3)4)

1) 0

C (comm.); -25

C (ext.);

DDQ

= 1.8 V

0.15 V;

2) All parameters assumes proper device initialization.

3) AC timing tests measured at 0.9 V.

4) The transition time is measured between

and

; all AC characteristics assume

= 1 ns.

Parameter

Symbol

- 7.5

Unit

Notes

min.

max.

Clock cycle time

CL = 3

7.5

CL = 2

9.5

Clock frequency

CL = 3

133

MHz

CL = 2

105

MHz

Access time from CLK

CL = 3

5.4

5)6)

5) Specified

and

parameters are measured with a 30 pF capacitive load only as shown below:

6) If

(CLK) > 1 ns, a value of (

/2 - 0.5) ns has to be added to this parameter.

CL = 2

6.0

Clock high-level width

2.5

Clock low-level width

2.5

Address, data and command input setup time

1.5

7) If

> 1 ns, a value of (

- 1) ns has to be added to this parameter.

Address, data and command input hold time

0.8

MODE REGISTER SET command period

MRD

DQ low-impedance time from CLK

1.0

DQ high-impedance time from CLK

3.0

7.0

Data out hold time

2.5

5)6)

DQM to DQ High-Z delay (READ Commands)

DQZ

DQM write mask latency

DQW

ACTIVE to ACTIVE command period

8) These parameter account for the number of clock cycles and depend on the operating frequency, as follows:

no. of clock cycles = specified delay / clock period; round up to next integer.

ACTIVE to READ or WRITE delay

RCD

ACTIVE bank A to ACTIVE bank B delay

RRD

ACTIVE to PRECHARGE command period

RAS

100k

WRITE recovery time

9) The write recovery time of

= 14 ns allows the use of one clock cycle for the write recovery time when

72 MHz.

With

> 72 MHz two clock cycles for

are mandatory. Infineon Technologies recommends to use two clock cycles for

the write recovery time in all applications.

PRECHARGE command period

Refresh period (4096 rows)

REF

Self refresh exit time

SREX

30 pF

I/O

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Electrical Characteristics

Data Sheet

V1.4, 2004-04-30

3.3

Operating Currents

Table 21

Maximum Operating Currents

1) 0

C (comm.); -25

C (ext.);

DDQ

= 1.8 V

0.15 V;

Recommended Operating Conditions unless otherwise noted

Parameter & Test Conditions

Symbol

Values

Unit

Notes

- 7.5

Operating current:
one bank: active / read / precharge, BL = 1,

RCmin

DD1

2)3)

2) These values are measured with

= 7.5 ns

3) All parameters are measured with no output loads.

Precharge power-down standby current:
all banks idle, CS

IHmin

, CKE

ILmax

inputs changing once every two clock cycles

DD2P

0.5

Precharge power-down standby current with clock stop:
all banks idle, CS

IHmin

, CKE

ILmax

, all inputs stable

DD2PS

0.35

Precharge non power-down standby current:
all banks idle, CS

IHmin

, CKE

IHmin

inputs changing once every two clock cycles

DD2N

Precharge non power-down standby current with clock stop:
all banks idle, CS

IHmin

, CKE

IHmin

, all inputs stable

DD2NS

1.0

Active power-down standby current:
one bank active, CS

IHmin

, CKE

ILmax

inputs changing once every two clock cycles

DD3P

1.0

Active power-down standby current with clock stop:
one bank active, CS

IHmin

, CKE

ILmax

, all inputs stable

DD3PS

0.5

Active non power-down standby current:
one bank active, CS

IHmin

, CKE

IHmin

inputs changing once every two clock cycles

DD3N

Active non power-down standby current with clock stop:
one bank active, CS

IHmin

, CKE

IHmin

, all inputs stable

DD3NS

1.5

Operating burst read current:
all banks active; continuous burst read,
inputs changing once every two clock cycles

DD4

2)3)

Auto-Refresh current:

RCmin

, "burst refresh",

inputs changing once every two clock cycles

DD5

Self Refresh current:
self refresh mode, CS

IHmin

, CKE

ILmax

, all inputs stable

DD6

see

Table 22

Deep Power Down current

DD7

HY[B/E]18L128160B[C/F]-7.5

128-Mbit Mobile-RAM

Electrical Characteristics

Data Sheet

V1.4, 2004-04-30

3.4

Pullup and Pulldown Characteristics

The above characteristics are specified under nominal process variation / condition
Temperature (

): Nominal = 50

DDQ

: Nominal = 1.80 V

Table 22

Self Refresh Currents

1)2)

1) 0

C (comm.); -25

C (ext.);

DDQ

= 1.8 V

0.15 V

2) The On-Chip Temperature Sensor (OCTS) adjusts the refresh rate in self refresh mode to the component's actual

temperature with a much finer resolution than supported by the 4 distinct temperature levels as defined by JEDEC for
TCSR. At production test the sensor is calibrated, and IDD6 max. current is measured at 85°C. Typ. values are obtained
from device characterization.

Parameter & Test Conditions

Max.

Temperature

Symbol

Values

Units

Notes

typ.

max.

Self Refresh Current:
Self refresh mode,
full array activation
(PASR = 000)

DD6

365

415

260

185

25 °C

165

Self Refresh Current:
Self refresh mode,
half array activation
(PASR = 001)

285

325

210

45 °C

155

140

Self Refresh Current:
Self refresh mode,
quarter array activation
(PASR = 010)

245

280

190

145

25 °C

130

Table 23

Half Drive Strength (Default) and Full Drive Strength

Voltage
(V)

Half Drive Strength (Default)

Full Drive Strength

Pull-Down Current (mA) Pull-Up Current (mA) Pull-Down Current (mA) Pull-Up Current (mA)

Nominal

Low

Nominal

High

Nominal

Low

Nominal

High

Nominal

Low

Nominal

High

Nominal

Low

Nominal

High

0.00

0.0

-19.7

-33.4

0.0

-39.3

-66.7

0.40

15.1

20.5

-18.8

-32.0

30.2

41.0

-37.6

-63.9

0.65

20.3

28.5

-18.2

-31.0

40.5

57.0

-36.4

-61.9

0.85

22.0

32.0

-17.6

-29.9

43.9

64.0

-35.1

-59.8

1.00

22.6

33.5

-16.7

-28.7

45.2

67.0

-33.3

-57.3

1.40

23.5

35.0

-9.4

-20.4

46.9

70.0

-18.8

-40.7

1.50

23.6

35.3

-6.6

-17.1

47.2

70.5

-13.2

-34.1

1.65

23.8

35.5

-1.8

-11.4

47.5

71.0

-3.5

-22.7

1.80

23.9

35.7

3.8

-4.8

47.7

71.4

7.5

-9.6

1.95

24.0

35.9

9.8

2.5

48.0

71.8

19.6

5.0

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HYE18L128160BF-75